The present invention relates to a plasma processing apparatus for generating a plasma and performing a predetermined process.
In the manufacture of a semiconductor device and flat panel display, plasma processing apparatuses are often used to perform processes such as formation of an oxide film, crystal growth of a semiconductor layer, etching, and ashing. One of the plasma processing apparatuses is called a parallel-plate plasma processing apparatus. A conventional parallel-plate plasma processing apparatus will be described by way of an example in which it is applied to an etching apparatus.
FIG. 10 includes views showing an arrangement of such an etching apparatus. As shown in FIG. 10(a), in this etching apparatus, the interior of a hermetically closeable process vessel 111 forms a process chamber 112. Exhaust ports 113 for evacuating the process chamber 112 to a predetermined vacuum degree are formed in the bottom of the process vessel 111. A gas supply nozzle 114 for supplying a process gas into the process chamber 112 is formed in the side wall of the process vessel 111.
An upper electrode 121 and susceptor 131 which form a pair of parallel-plate electrodes are arranged in the process chamber 112. The upper electrode 121 is connected through a feeder rod 122 to an RF power supply 124 which supplies power for generating a plasma. A matcher 123 is interposed in the feeder rod 122.
The susceptor 131 is connected to an RF power supply 134, which supplies power for applying a bias across the susceptor 131 and upper electrode 121, through a feeder rod 132. A matcher 133 is arranged midway along the feeder rod 132.
An electrostatic chuck 141 is formed on the support surface of the susceptor 131. As shown in FIG. 10(b), the electrostatic chuck 141 is formed of two insulating films 141A and 141B and a conductive film 141C sandwiched between them. The conductive film 141C of the electrostatic chuck 141 is connected to a variable DC high-voltage power supply 142 provided outside the process vessel 111. An annular focus ring 143 is formed on the periphery of the support surface of the susceptor 131 so as to surround the electrostatic chuck 141.
FIG. 11 is a circuit diagram of a 3D circuit extending from a plasma bulk P to a bias power supply 134. In FIG. 11, reference symbol C1 denotes a capacitance formed on an ion sheath SH around the plasma bulk P; C2, a capacitance formed in a gate oxide film formed on a wafer W, C3, a capacitance formed in the gap between the wafer W and electrostatic chuck 141; and C4 and C5, capacitances respectively formed in the insulating films 141A and 141B of the electrostatic chuck 141. Reference symbol R denotes a resistance of the wafer W; and W′, an element or interconnection formed on the wafer W.
FIG. 12 includes graphs showing voltage changes at the respective portions of the 3D circuit shown in FIG. 11. FIG. 12(a) shows a voltage change of the matcher 133 on the power supply 134 side (point a of FIG. 11), FIG. 12(b) shows a voltage change of the matcher 133 on the susceptor 131 side (point b of FIG. 11), and FIG. 12(c) shows a voltage change of an etching surface (point c of FIG. 11) as the surface of the wafer W.
When a plasma is generated, a difference in mobility between the electrons and ions in the plasma generates a negative DC voltage Vdc on the surface of the ion sheath SH. The value of the DC voltage Vdc changes depending on the process conditions, and can become, e.g., about −700 V. In this case, when the bias RF power supply 134 outputs, e.g., an AC voltage with an amplitude of 750 V as shown in FIG. 12(a), the voltage of the etching surface (point c) of the wafer W becomes a voltage obtained by superposing the DC voltage Vdc on the above AC voltage, as shown in FIG. 12(c).
However, the voltage of the matcher 133 on the susceptor 131 side (point b) is almost the same as that on the power supply 134 side, as shown in FIG. 12(b), and no DC voltage is substantially applied across the matcher 133. Hence, the DC voltage Vdc is mostly applied from the wafer W to the electrostatic chuck 141. The capacitance C2 of the wafer W is sufficiently smaller than the capacitances C4 and C5 of the electrostatic chuck 141. Thus, a considerably high voltage is applied across the wafer W.
In this manner, when a large potential difference occurs between the upper and lower surfaces of the wafer W, the gate oxide film or the like formed on the wafer W is damaged to break the element. This problem arises not only when the plasma processing apparatus is applied to an etching apparatus but also is common in any plasma processing apparatus.